在ISE12.4版本中，用ISE自带的综合工具XST综合时出现以下错误：
ERROR:Xst:899 - "tt_encoder.v" line 46: The logic for <code_valid> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "tt_encoder.v" line 47: The logic for <code_msb> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "tt_encoder.v" line 48: The logic for <code_value> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
源代码如下：
always@(posedge clk or negedge rst_n)
begin
if(!rst_n || !input_valid)
begin
行46 code_valid <= 0;
行47 code_msb <= 0;
行48 code_value <= 0;
end
else
begin
解决分析：
Verilog的always块中，ISE12.4的综合工具XST不支持复杂的条件检查（其他版本的ISE可能支持）。应将代码修改如下：
always@(posedge clk or negedge rst_n)
begin
// if(!rst_n || !input_valid)
if(!rst_n)
begin
code_valid <= 0;
code_msb <= 0;
code_value <= 0;
end
else if(!input_valid)
begin
code_valid <= 0;
code_msb <= 0;
code_value <= 0;
end
else
begin
或者将所用器件改一下：原来为family Virtex5 现在改为：Virtex6。
