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它分析网表，时钟网络连接和现有的时序约束，识别设计上缺少的时序约束。
向导包括11个页面涵盖三类约束：
•时钟
°主时钟Primary clocks
°生成时钟Generated clocks
°转发时钟Forwarded clocks
°外部反馈延迟External feedback delays
•输入输出端口
°输入延迟Input delays
°输出延迟Output delays
°组合延迟Combinatorial delays
•时钟域交叉
°物理专用时钟组Physically exclusive clock groups
°无交互的逻辑专用时钟组Logically exclusive clock groups with no interaction
°有交互的逻辑专用时钟组Logically exclusive clock groups with interaction
°异步时钟域交叉Asynchronous clock domain crossings
