verilog 计数器

counter.v

`timescale 1 ns/10 ps 
module con (clk,res,y);

input        clk;
input        res;
output[7:0]  y;
reg[7:0]     y;       //触发器定义成reg变量;
wire[7:0]    sum;     //+1 运算结果

assign       sum=y+1; //组合逻辑部分

always@(posedge clk or negedge res)

if (~res) begin 
    y<=0;  //res 为低时y寄存器复位
    end
else begin 

   y<=sum;  // y得到sum值,触发器正常工作时候

end 


endmodule

stimulus_tb.v

//-----testbench  of count-----

`timescale 1 ns/10 ps 
module comp_conv_tb;

reg        clk,res;

wire[7:0]  y;
//异名例化
con  con (.clk(clk),
          .res(res),
          .y(y));
 
initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,comp_conv_tb);
     

         clk<=0 ;res<=0;
    #17 res<=1;
    # 6000 $stop;         
end

always #5 clk=~clk;
 
endmodule

compile.sh

#!/bin/bash
echo "开始编译"

iverilog counter.v stimulus_tb.v -o fn

#./invet

echo "编译完成"
vvp -n fn -lxt2
echo "生成波形文件"
cp test.vcd wave.lxt
echo "打开波形文件"
gtkwave wave.lxt