[组合逻辑]
源程序：可以认为 led_test 就是一个芯片
module led_test(a, b, c, out);
input a; // 输入信号 input b; // 输入信号 input c; // 输入信号
//output [7:0]out; // 由于要用到 always 程序块中，需要声明为 reg 类型 // 如果不是 reg 类型则会报错 Procedural Assignment error at led_test.v(12): // object "out" on left-hand side of assignment must have a variable data type output reg [7:0]out; // 输出信号
always@(a, b, c)begin case({a, b, c}) 3'b000 : out = 8'b0000_0001; 3'b001 : out = 8'b0000_0010; 3'b010 : out = 8'b0000_0100; 3'b011 : out = 8'b0000_1000; 3'b100 : out = 8'b0001_0000; 3'b101 : out = 8'b0010_0000; 3'b110 : out = 8'b0100_0000; 3'b111 : out = 8'b1000_0000; endcase end
endmodule
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仿真程序：
`timescale 1ns/1ns // 延时时间单位/仿真精度 module led_test_tb;
reg a, b, c; wire[7:0] out;
led_test u1(.a(a), .b(b), .c(c), .out(out)); // 将端口(IO口)连接到 led_test 芯片中
initial begin
a = 0; b = 0; c = 0; // 设置端口(IO口)的电平状态 #200; a = 0; b = 0; c = 1; #200; a = 0; b = 1; c = 0; #200; a = 0; b = 1; c = 1; #200; a = 1; b = 0; c = 0; #200; a = 1; b = 0; c = 1; #200; a = 1; b = 1; c = 0; #200; a = 1; b = 1; c = 1; #200; $stop; // 停止执行
end
endmodule
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知识点总结：
1、always 里面的变量必须是 reg 类型，否则会报如下错误
2、从仿真的角度来看，out 输出的电平并不是理想的。
放大其中，从 00000001 跳变到 00000010 中间还有一个 00000000
从 00000001 变化到 0000010 有两个bit会发生变化，由于电路结构关系，它们有可能不会同时变化，有可能bit1最开始变化，也有可能bit0最开始变化。
还有另外一种情况：
3、如果已经运行了仿真程序，则会报如下错误
作业：实现一个4-16 译码器
源程序：
/* 4-16 译码器 */ module led_test(a, b, c, d, out);
input a, b, c, d; output reg[15:0] out;
always@(a, b, c, d)begin
case({a, b, c, d}) 4'b0000 : out = 16'b0000_0000_0000_0001; 4'b0001 : out = 16'b0000_0000_0000_0010; 4'b0010 : out = 16'b0000_0000_0000_0100; 4'b0011 : out = 16'b0000_0000_0000_1000; 4'b0100 : out = 16'b0000_0000_0001_0000; 4'b0101 : out = 16'b0000_0000_0010_0000; 4'b0110 : out = 16'b0000_0000_0100_0000; 4'b0111 : out = 16'b0000_0000_1000_0000; 4'b1000 : out = 16'b0000_0001_0000_0000; 4'b1001 : out = 16'b0000_0010_0000_0000; 4'b1010 : out = 16'b0000_0100_0000_0000; 4'b1011 : out = 16'b0000_1000_0000_0000; 4'b1100 : out = 16'b0001_0000_0000_0000; 4'b1101 : out = 16'b0010_0000_0000_0000; 4'b1110 : out = 16'b0100_0000_0000_0000; 4'b1111 : out = 16'b1000_0000_0000_0000; endcase
end
endmodule
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仿真程序：
`timescale 1ns/1ns module led_test_tb;
reg a, b, c, d; wire[15:0] out;
led_test u1(.a(a), .b(b), .c(c), .d(d), .out(out));
initial begin a = 0; b = 0; c = 0; d = 0; #200; a = 0; b = 0; c = 0; d = 1; #200; a = 0; b = 0; c = 1; d = 0; #200; a = 0; b = 0; c = 1; d = 1; #200; a = 0; b = 1; c = 0; d = 0; #200; a = 0; b = 1; c = 0; d = 1; #200; a = 0; b = 1; c = 1; d = 0; #200; a = 0; b = 1; c = 1; d = 1; #200; a = 1; b = 0; c = 0; d = 0; #200; a = 1; b = 0; c = 0; d = 1; #200; a = 1; b = 0; c = 1; d = 0; #200; a = 1; b = 0; c = 1; d = 1; #200; a = 1; b = 1; c = 0; d = 0; #200; a = 1; b = 1; c = 0; d = 1; #200; a = 1; b = 1; c = 1; d = 0; #200; a = 1; b = 1; c = 1; d = 1; #200; $stop; end endmodule
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仿真波形：
