[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is en_dct2d_reg_i_1_n_0. Please evaluate your design.
解决办法是写约束条件：
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets en_dct2d_reg_i_1_n_0];
