5.设计一个11分频的分频器，要求输出占空比为50%，不能使用PLL
法一
author : Mr.Mao
e-mail : 2458682080@qq.com
module div11x
(
input clk,
input reset_n,
output q
);
reg [3:0] cnt;
reg x_p,x_n;
always @(posedge clk,negedge reset_n)
if(!reset_n)
cnt <= 0;
else if(cnt < 11-1)
cnt <= cnt + 1'b1;
else
cnt <= 0;
always @(posedge clk,negedge reset_n)
if(!reset_n)
x_p <= 0;
else if(cnt < 11/2)
x_p <= 1;
else
x_p <= 0;
always @(negedge clk,negedge reset_n)
if(!reset_n)
x_n <= 0;
else
x_n <= x_p;
assign q = x_p | x_n;
endmodule
法二
author : Mr.Mao
e-mail : 2458682080@qq.com
module Fre_div_11(clk , clk_out, rst_n) ; //11分频
input clk,rst_n ; //奇数分频需要对上升沿和下降沿分别采样，得到占空比为50%的时钟
output clk_out ;
reg [3:0] cnt_p, cnt_n;
reg clk_p, clk_n;
always@(posedge clk or negedge rst_n) //上升沿触发
begin
if(!rst_n) begin cnt_p <= 0; clk_p <=0; end
else
begin
if(cnt_p == 10)
cnt_p <= 0 ; //计数清零
else
cnt_p <= cnt_p + 1 ;
if(cnt_p == 4)
clk_p <=~ clk_p ; //时钟翻转
else if(cnt_n == 9)
clk_p <=~ clk_p ; //时钟翻转
end
end
always@(negedge clk or negedge rst_n) //下降沿触发
begin
if(!rst_n) begin cnt_n <= 0; clk_n <= 0 ; end
else
begin
if(cnt_n == 10)
cnt_n <= 0 ; //计数清零
else
cnt_n <= cnt_n + 1 ;
if(cnt_n == 4)
clk_n <= ~ clk_n ; //时钟翻转
else if(cnt_n == 9)
clk_n <= ~ clk_n ; //时钟翻转
end
end
assign clk_out = clk_n | clk_p ; //两输出波形相或运算，assign只能是net型
endmodule
