因为是5分频 所以pcnt=2 为1 pcnt=4 为0
如果是7分频 则 pcnt=3 为1 pcnt=6 为0
还想着用怎么pos_flag 作上升沿 neg_flag 作下降沿 没想到最后运用了或运算 。。。。。
always@(posedge clk) begin if (rst) begin pos_flag<=0; end else if((pcnt==3)&(pcnt==4)) begin pos_flag<=1; end else begin pos_flag<=0; end end
module fenpin_5( input wire clk, input wire rst, output wire clk5); reg [2:0] pcnt; reg [2:0] ncnt; reg pos_flag; reg neg_flag; always@(posedge clk) begin if(rst) pcnt<=0; else if(pcnt==4) pcnt<=0; else pcnt<=pcnt+1'b1; end always @(negedge clk) begin if(rst) ncnt<=0; else if(ncnt==4) ncnt<=0; else ncnt<=ncnt+1'b1; end always@(posedge clk) begin if (rst) begin pos_flag<=0; end else if(pcnt==2) begin pos_flag<=1; end else if(pcnt==4) begin pos_flag<=0; end end always@(negedge clk) begin if (rst) begin pos_flag<=0; end else if(ncnt==2) begin neg_flag<=1; end else if (ncnt==4) begin neg_flag<=0; end end assign clk5 =pos_flag|neg_flag ; endmodule
`timescale 1ns/1ns module tb_fenpin_5(); reg clk,rst; wire clk5; initial begin clk=0; rst=1; #100 rst=0; end always #10 clk=~clk; fenpin_5 tb_fenpin_5_inst( .clk(clk), .rst(rst), .clk5(clk5)); endmodule