This design element is automatically inserted (inferred) by the synthesis tool to any signal directly connected to a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.
However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly to the associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.
Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to change the default behavior of the component.

这个设计元素由综合工具自动插入（inferred）到与设计的顶层输入或输入输出端口直接连接的任何信号。（翻译的太蹩脚了，意思也就是这个IBUF通过综合工具推断，被插入到任何输入信号上，或者是一个输入输出（in-out）信号。）

您通常应该让综合工具推断出这个缓冲区。
但是，如果需要，可以将其实例化到设计中。为此，将输入端口（I）直接连接到相关的顶级输入或输入输出端口，并将输出端口（O）连接到该端口提供的逻辑。修改任何必要的通用映射（VHDL）或命名参数值赋值（Verilog）以更改组件的默认行为。

说简单很简单，就不用你管，你知道有这个东西就好了，他就是与输入信号相连接的一个输入缓冲，这玩意很重要，在FPGA电路中几乎可以说是必须用。

如果非得自己实例化，我也给出模板：

Verilog Instantiation Template
// IBUF: Single-ended Input Buffer
// All devices
// Xilinx HDL Libraries Guide, version 11.2
IBUF #(
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
// the buffer: "0"-"12" (Spartan-3E)
// "0"-"16" (Spartan-3A)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
// register: "AUTO", "0"-"6" (Spartan-3E)
// "AUTO", "0"-"8" (Spartan-3A)
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
)IBUF_inst (
.O(O), // Buffer output
.I(I) // Buffer input (connect directly to top-level port)
);
// End of IBUF_inst instantiation

IBUFDS

这个原语就很重要了，我曾经在工程中遇到过它，当时我很纳闷，这到底是个啥玩意，一系列类似的buff让我很头疼

这是一个差分转单端的Buffer而已，用途就是将差分信号转换成单端信号。

如下：

【FPGA】Buffer专题介绍（二）_ios_02

This design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a design level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to help improve signal integrity and reduce external components.

该设计元素是一个支持低电压差分信号的输入缓冲器。在IBUFDS中，设计级接口信号表示为两个不同的端口（I和IB），一个视为“主”，另一个视为“从”。主机和从机是相同逻辑信号的相位相反（例如，MYNET_P和MYNET_N）。可选的，可编程差分端接功能可用于帮助改善信号完整性并减少外部元件。

（谷歌翻译有时候还可以，差不多我就不修改了！）

【FPGA】Buffer专题介绍（二）_ide_03

这个Buffer就需要自己例化了。

例化模板：

Verilog Instantiation Template
// IBUFDS: Differential Input Buffer
// Virtex-4/5, Spartan-3/3E/3A
// Xilinx HDL Libraries Guide, version 11.2
IBUFDS #(
.CAPACITANCE("DONT_CARE"), // "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)
.DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A)
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
// the buffer: "0"-"12" (Spartan-3E)
// "0"-"16" (Spartan-3A)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
// register: "AUTO", "0"-"6" (Spartan-3E)
// "AUTO", "0"-"8" (Spartan-3A)
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_inst (
.O(O), // Buffer output
.I(I), // Diff_p buffer input (connect directly to top-level port)
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
);
// End of IBUFDS_inst instantiation

IBUFG

【FPGA】Buffer专题介绍（二）_ide_04

专用输入时钟缓冲器（ Dedicated Input Clock Buffer）

这个原语的使用也是通过综合工具推断，需要的时候自动添加的。同样，你也可以例化来用（就怕你不会用，哈哈）。

【FPGA】Buffer专题介绍（二）_原语_05

下面的介绍还不错：

The IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA’s global clock routing resources. The IBUFG provides dedicated connections to the DCM, PLL, or BUFG resources. providing the minimum amount of clock delay and jitter to the device. The IBUFG input can only be driven by the global clock (GC) pins.

IBUFG是器件的专用输入，应用于将输入时钟连接到FPGA的全局时钟布线资源。 IBUFG提供与DCM，PLL或BUFG资源的专用连接。为器件提供最小量的时钟延迟和抖动。 IBUFG输入只能由全局时钟（GC）引脚驱动。

Verilog Instantiation Template
// IBUFG: Global Clock Buffer (sourced by an external pin)
// All FPGAs
// Xilinx HDL Libraries Guide, version 11.2
IBUFG #(
.IOSTANDARD("DEFAULT"),
.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for
// the buffer: "0"-"12" (Spartan-3E)
// "0"-"16" (Spartan-3A)
) IBUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input (connect directly to top-level port)
);
// End of IBUFG_inst instantiation

IBUFGDS

【FPGA】Buffer专题介绍（二）_ios_06

差分信号专用输入时钟缓冲器和可选延迟（Differential Signaling Dedicated Input Clock Buffer and Optional Delay）

这个Buffer需要自己例化来使用。

This design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or MMCM. In IBUFGDS, a design-level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to help improve signal integrity and reduce external components. Also available is a programmable delay is to assist in the capturing of incoming data to the device.

该设计元素是专用差分信号输入缓冲器，用于连接时钟缓冲器（BUFG）或MMCM。在IBUFGDS中，设计级接口信号表示为两个不同的端口（I和IB），一个视为“主”，另一个视为“从”。主机和从机是相同逻辑信号的相位相反（例如，MYNET_P和MYNET_N）。可选的，可编程差分端接功能可用于帮助改善信号完整性并减少外部元件。还可以使用可编程延迟来帮助捕获到设备的输入数据。

【FPGA】Buffer专题介绍（二）_ios_07

Verilog Instantiation Template
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
// Virtex-4/5, Spartan-3/3E/3A
// Xilinx HDL Libraries Guide, version 11.2
IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A)
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for
// the buffer: "0"-"12" (Spartan-3E)
// "0"-"16" (Spartan-3A)
) IBUFGDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input
.IB(IB) // Diff_n clock buffer input
);
// End of IBUFGDS_inst instantiation