目录
背景
CLB布局（CLB Arrangement）
ASMBL Architecture
CLB Slices
CLB/Slice Configurations
Slice Description
Look-Up Table (LUT)
Storage Elements
Control Signals
背景
本博文是上篇博文的续集：Xilinx® 7 series FPGAs CLBs专题介绍（一），由于博文太长了阅读起来不太方便，所以这篇博文单独出来。
在数据手册上看到这个简单地总结目录还是不错的，这里贴出来并且按照这个目录来进行分别介绍：
This chapter provides a detailed view of the 7 series FPGAs CLB architecture. These details can be useful for design optimization and verification, but are not necessary for initiating a design. This chapter includes:
• CLB Arrangement
Overview of slice locations and features within the CLB
• Slice Description
Complete details of SLICEM and SLICEL
• Look-Up Table (LUT)
Description of the logical function generators
• Storage Elements
Description and controls for the latches and flip-flops
• Distributed RAM (Available in SLICEM Only)
SLICEM ability to use LUTs as writable memory
• Shift Registers (Available in SLICEM Only)
SLICEM ability to use LUTs as shift registers
• Multiplexers
Dedicated gates for combining LUTs into wide functions
• Carry Logic
Dedicated gates and cascading to implement efficient arithmetic functions.
本章提供了7系列FPGA CLB架构的详细视图。 这些细节可用于设计优化和验证，但不是启动设计所必需的。
CLB布局（CLB Arrangement）主要讲述CLB中的Slice的位置以及特征的概述；
The CLBs are arranged in columns in the 7 series FPGAs. The 7 series is the fourth generation to be based on the unique columnar approach provided by the ASMBL™ architecture.
CLB在7系列FPGA中按列排列。 7系列是第四代基于ASMBL™架构提供的独特柱状方法。
ASMBL Architecture
Xilinx created the Advanced Silicon Modular Block (ASMBL) architecture to enable FPGA platforms with varying feature mixes optimized for different application domains. Through this innovation Xilinx offers a greater selection of devices, enabling customers to select the FPGA with the right mix of features and capabilities for their specific design.
Figure 2-1 provides a high-level description of the different types of column-based resources.
Xilinx创建了高级硅模块（ASMBL）架构，使FPGA平台具有针对不同应用领域优化的各种功能组合。 通过这项创新，赛灵思提供了更多的器件选择，使客户能够根据特定设计选择具有适当特性和功能的FPGA。图2-1提供了不同类型的基于列的资源的高级描述。
从上图可以看出，通过高级硅模块（ASMBL）架构（Architecture），在不同的领域（上图为领域A、B、C）集成了不同的功能块，使之适合于不同领域的不同需求，例如根据这些差别，Xilinx将7系列的FPGA分为了4种小的系列，每个系列又有很多中不同的型号的FPGA。
Xilinx® 7 series FPGAs comprise four FPGA families:
- Spartan®-7 Family
- Artix®-7 Family
- Kintex®-7 Family
- Virtex®-7 Family
例如virtex_7中有xc7vx690t等，更多分法见：Xilinx® 7 series FPGAs Overview，或官方数据手册：http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf。
CLB Slices
A CLB element contains a pair of slices, and each slice is composed of four 6-input LUTs and eight storage elements.
• SLICE(0) – slice at the bottom of the CLB and in the left column
• SLICE(1) – slice at the top of the CLB and in the right column
These two slices do not have direct connections to each other, and each slice is organized as a column. Each slice in a column has an independent carry chain.
一个CLB包含一对slice，并且每个slice由4个6输入的LUT和8个存储器件。
SLICE（0）：位于CLB的底部且在左边一列，又称为SLICEL；
SLICE（1）：位于CLB的顶部且在右边一列，又称为SLICEM；
这两个SLICE相互之间没有直接的连接，并且每一个SLICE都被组织为一列。每个SLICE都有一个独立的进位链。
如下图示：
上图中的X0Y1、X0Y0等都是什么意思呢？
简单地说X以及后面的一个数字代表的是一个slice的列的位置，从左往右开始计数（0,1,2,3，...）；
Y以及后面的数字代表的是一个slice的行的位置，从下往上依次计数（0,1...）;
下面是数据手册原话：
The Xilinx tools designate slices with these definitions:
• An “X” followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc.
• A “Y” followed by a number identifies a row of slices. The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom.Xilinx工具使用以下定义指定切片：
•后跟数字的“X”标识一对中每个slice的位置以及slice的列位置。 “X”数从序列0,1（第一个CLB列）的底部开始计数切片; 2,3（第二个CLB栏）; 等等
•后跟数字的“Y”表示一行切片。 CLB中的数字保持不变，但从底部开始，从一个CLB行到下一个CLB行依次计数。
CLB/Slice Configurations
Table 2-1 summarizes the logic resources in one CLB. Each SLICEM LUT can be configured as a look-up table, distributed RAM, or a shift register.
表2-1总结了一个CLB中的逻辑资源。 每个SLICEM LUT都可以配置为查找表，分布式RAM或移位寄存器。
表的下面还贴心的重复了这个问题：仅限SLICEM，SLICEL没有分布式RAM或移位寄存器。
Slice Description
Every slice contains:
• Four logic-function generators (or look-up tables)
• Eight storage elements
• Wide-function multiplexers
• Carry logic
These elements are used by all slices to provide logic, arithmetic, and ROM functions. In addition, some slices support two additional functions: storing data using distributed RAM and shifting data with 32-bit registers. Slices that support these additional functions are called SLICEM; others are called SLICEL.每个切片包含：
•四个逻辑函数发生器（或查找表）
•八个存储元件
•宽功能多路复用器
•进位逻辑
所有slice都使用这些元素来提供逻辑，算术和ROM功能。 此外，一些slice支持两个附加功能：使用分布式RAM存储数据和使用32位寄存器移位数据。 支持这些附加功能的slice称为SLICEM; 其他人被称为SLICEL。
Look-Up Table (LUT)
The function generators in 7 series FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement:
• Any arbitrarily defined six-input Boolean function
• Two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs
• Two arbitrarily defined Boolean functions of 3 and 2 inputs or less
A six-input function uses:
• A1-A6 inputs
• O6 output
Two five-input or less functions use:
• A1–A5 inputs
• A6 driven High
• O5 and O6 outputs
7系列FPGA中的函数发生器实现为六输入查找表（LUT）。 对于slice（A，B，C和D）中的四个函数发生器中的每一个，存在六个独立输入（A输入-A1至A6）和两个独立输出（O5和O6）。 函数发生器可以实现：
•任意定义的六输入布尔函数
•两个任意定义的五输入布尔函数，只要这两个函数共享公共输入
•两个任意定义的3和2输入或更少的布尔函数
六输入功能使用：
•A1-A6输入
•O6输出
两个五输入或更少的功能使用：
•A1-A5输入
•A6驱动高
•O5和O6输出
The propagation delay through a LUT is independent of the function implemented. Signals from the function generators can:
• Exit the slice (through A, B, C, D output for O6 or AMUX, BMUX, CMUX, DMUX output for O5)
• Enter the XOR dedicated gate from an O6 output
• Enter the carry-logic chain from an O5 output
• Enter the select line of the carry-logic multiplexer from O6 output
• Feed the D input of the storage element
• Go to F7AMUX/F7BMUX wide multiplexers from O6 output
In addition to the basic LUTs, slices contain three multiplexers (F7AMUX, F7BMUX, and F8MUX). These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice.
• F7AMUX: Used to generate seven input functions from LUTs A and B
• F7BMUX: Used to generate seven input functions from LUTs C and D
• F8MUX: Used to combine all LUTs to generate eight input functions.
Functions with more than eight inputs can be implemented using multiple slices. There are no direct connections between slices to form function generators greater than eight inputs within a CLB.通过LUT的传播延迟与实现的功能无关。
来自函数发生器的信号可以：
•退出切片（通过A，B，C，D输出为O6或AMUX，BMUX，CMUX，DMUX输出为O5）
•从O6输出进入XOR专用门
•从O5输出进入进位逻辑链
•从O6输出进入进位逻辑多路复用器的选择线
•输入存储元件的D输入
•从O6输出转到F7AMUX / F7BMUX宽多路复用器
除基本LUT外，Slice还包含三个多路复用器（F7AMUX，F7BMUX和F8MUX）。这些多路复用器用于组合多达四个函数发生器，以提供片中七个或八个输入的任何功能。
•F7AMUX：用于从LUT A和B生成七个输入功能
•F7BMUX：用于从LUT C和D生成七个输入功能
•F8MUX：用于组合所有LUT以生成八个输入功能。
可以使用多个切片实现具有八个以上输入的功能。切片之间没有直接连接，以在CLB内形成大于8个输入的函数发生器。
Storage Elements
There are eight storage elements per slice. Four can be configured as either edge-triggered D-type flip-flops or level-sensitive latches.
The D input can be driven directly by a LUT output via AFFMUX, BFFMUX, CFFMUX, or DFFMUX, or by the BYPASS slice inputs bypassing the function generators via AX, BX, CX, or DX input. When configured as a latch, the latch is transparent when the CLK is Low.
每个slice有8个存储元件。其中4个可以被配置成沿触发的D触发器或电平触发的锁存器。
D输入可由LUT输出通过AFFMUX，BFFMUX，CFFMUX或DFFMUX直接驱动，或通过BYPASS slice（？？？这是啥？）输入绕过函数发生器（LUT）通过AX，BX，CX或DX输入。 当配置为锁存器时，当CLK为低电平时，锁存器是透明的。
There are four additional storage elements that can only be configured as edge-triggered D-type flip-flops.
The D input can be driven by the O5 output of the LUT or the BYPASS slice inputs via AX, BX, CX, or DX input. When the original four storage elements are configured as latches, these four additional storage elements cannot be used.
另外4个存储元件只能被配置成沿触发的D触发器。D输入可以由LUT的输出O5驱动，或者BYPASS slice输入通过AX，BX，CX或DX输入。当原来的4个存储元件被配置成锁存器时，另外4个额外的存储元件就不能被使用。
上面的关于D输入的驱动问题可能有些难理解，给出这张图帮助一下理解，第一个图是只能配置成触发器的图，第二个是：既可以配置成触发器又可以配置成锁存器的图。
Control Signals
The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice. When one flip-flop in a slice has SR or CE enabled, the other flip-flops used in the slice also have SR or CE enabled by the common signal. Only the CLK signal has programmable polarity. Any inverter placed on the clock signal is automatically absorbed. The CE and SR signals are active-High.
控制信号时钟（CLK），时钟使能（CE）和置位/复位（SR）对于一个片中的所有存储元件是公共的。 当切片中的一个触发器启用SR或CE时，切片中使用的其他触发器也具有由公共信号启用的SR或CE。 只有CLK信号具有可编程极性。 放置在时钟信号上的任何反相器都会被自动吸收。 CE和SR信号为高电平有效。
These initialization options are available for storage elements:
• SRLOW: Synchronous or asynchronous Reset when CLB SR signal is asserted• SRHIGH: Synchronous or asynchronous Set when CLB SR signal is asserted
• INIT0: Asynchronous Reset on power-up or global Set/Reset
• INIT1: Asynchronous Set on power-up or global Set/Reset
The SR signal forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic High at the storage element output when SR is asserted, while SRLOW forces a logic Low at the storage element output
这些初始化选项对存储元件有效：
• SRLOW: 当CLB SR信号有效时，同步或异步复位；
• SRHIGH: 当CLB SR信号有效时，同步或异步置位。
•INIT0：上电或全局置1 /复位时的异步复位
•INIT1：上电或全局置1 /复位时异步置位
SR信号强制存储元件进入SRHIGH或SRLOW属性指定的状态。 当SR被置位时，SRHIGH强制存储元件输出处的逻辑高电平，而SRLOW强制存储元件输出处的逻辑低电平
下表为真值表：
