Verilog 基本电路5-38译码器

module DC_38(
  input  a,
  input  b,
  input  c,
  output reg [7:0]  led
  );
  always@(a,b,c)begin
    case({a,b,c})
      3'b000:led = 8'b0000_0001;
      3'b001:led = 8'b0000_0010;
      3'b010:led = 8'b0000_0100;
      3'b011:led = 8'b0000_1000;
      3'b100:led = 8'b0000_0001;
      3'b101:led = 8'b0000_0001;
      3'b110:led = 8'b0000_0001;
      3'b111:led = 8'b0000_0001;
    endcase
  end 
endmodule