1、General description
概述
The TJA1044 is part of the Mantis family of high-speed CAN transceivers. It provides an
interface between a Controller Area Network (CAN) protocol controller and the physical
two-wire CAN bus. The transceiver is designed for high-speed CAN applications in the
automotive industry, providing the differential transmit and receive capability to (a
microcontroller with) a CAN protocol controller.
TJA1044是Mantis系列高速CAN收发器的一个成员。它提供了一个控制器局域网（CAN）协议控制器和物理CAN总线双线【CAN-H,CAN-L】之间的接口。该收发机是为汽车行业中的高速CAN应用而设计的，为带有CAN协议控制器的微控制器提供差分发送和接收能力。
The TJA1044 offers a feature set optimized for 12 V automotive applications, with
significant improvements over NXP's first- and second-generation CAN transceivers, such
as the TJA1040 and TJA1042, and excellent ElectroMagnetic Compatibility (EMC)
performance.
TJA1044提供了针对12 V汽车应用优化后的功能集，与NXP的第一代和第二代CAN收发器相比有了重大改进，例如TJA1040和TJA1042，并且具有良好的电磁兼容性（EMC）性能。
Additionally, the TJA1044 features:
• Ideal passive behavior to the CAN bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability
• Excellent EMC performance at speeds up to 500 kbit/s, even without a common mode
choke
• TJA1044GT/3 and TJA1044GTK/3 can be interfaced directly to microcontrollers with
supply voltages from 3 V to 5 V
此外，TJA1044还具有以下特点：
•电源电压关闭时，CAN总线拥有理想的被动行为
•具有总线唤醒功能的极低电流待机模式
•即使没有共模，也能在高达500 kbit/s的传输速度时拥有优异的EMC性能
•TJA1044GT/3和TJA1044GTK/3可以直接连接到电源电压从3伏到5伏的微控制器
These features make the TJA1044 an excellent choice for all types of HS-CAN networks,
in nodes that require a low-power mode with wake-up capability via the CAN bus.
The TJA1044 implements the CAN physical layer as defined in ISO 11898-2:2016 and
SAE J2284-1 to SAE J2284-5. The TJA1044T is specified for data rates up to 1 Mbit/s.
Additional timing parameters defining loop delay symmetry are specified for the other
variants. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 5 Mbit/s.
这些特性使得TJA1044成为所有HS-CAN网络类型的最佳选择，这些HS-CAN网络是需要通过CAN总线具有唤醒功能的低功耗模式的网络节点。TJA1044实现了ISO 11898-2:2016和
SAE J2284-1至SAE J2284-5定义的CAN物理层协议。TJA1044T可以将数据速率提高到高达1 Mbit/s。TJA1044T的另一个变种可以定义环路延迟对称性的附加定时参数。这种变种实现可以在CAN FD快速阶段实现可靠通信，CANFD的传输数据速率可以高达5 Mbit/s。
2. Features and benefits
特点和优点
2.1 General
概述
1)Fully ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant
2) Very low-current Standby mode with host and bus wake-up capability
3) Optimized for use in 12 V automotive systems
4) EMC performance satisfies 'Hardware Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications’, Version 1.3, May 2012.
5) AEC-Q100 qualified
6) Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
7）VIO input on TJA1044x/3 variants allows for direct interfacing with 3 V to 5 V
microcontrollers. Variants without a VIO pin can interface with 3.3 V and 5 V-supplied
microcontrollers, provided the microcontroller I/Os are 5 V tolerant.
8） Both VIO and non-VIO variants are available in SO8 and leadless HVSON8 (3.0
mm *3.0 mm) packages; HVSON8 with improved Automated Optical Inspection (AOI)
capability.
1)完全符合ISO 11898-2:2016和SAE J2284-1至SAE J2284-5标准
2) 具有主机和总线唤醒功能的极低电流待机模式
3)用于12伏汽车系统时进行了优化
4） EMC性能满足客户对《汽车应用中的LIN、CAN和FlexRay的硬件接口要求》，1.3版，2012年5月。
5） AEC-Q100合格
6）深绿色产品（无卤素且符合有害物质(RoHS)限制）
7） TJA1044x/3变种型号上的VIO输入引脚允许与供电电压为3 V至5 V的微控制器直接连接。没有VIO引脚的变种型号可以与供电电压为3.3 V和5 V的微控制器直接连接，前提是微控制器I/O可以承受5V。
8） 有VIO引脚的芯片和没有VIO引脚的变种芯片均提供SO8和无铅HVSON8（3.0毫米*3.0毫米）封装；HVSON8封装具有改进的自动光学检测（AOI)特性。
2.2 Predictable and fail-safe behavior
可预测的故障安全行为
1）Functional behavior predictable under all supply conditions
2）Transceiver disengages from bus when not powered (zero load)
3）Transmit Data (TXD) and bus dominant time-out functions
4） Internal biasing of TXD and STB input pins
1）功能行为在所有供电条件下都是可预测的
2）未通电（零负载）时，收发器与总线断开
3）传输数据（TXD）和总线显性超时功能
4）TXD和STB输入引脚的内部电压偏置
2.3 Protection
保护
1）High ESD handling capability on the bus pins (8 kV IEC and HBM)
2） Bus pins protected against transients in automotive environments
3） Undervoltage detection on pins VCC and VIO
4） Thermally protected
1）总线引脚上的高ESD处理能力（8 kV IEC和HBM）
2）在汽车环境中防止瞬变的总线引脚
3） 引脚VCC和VIO上的欠压检测
4）热保护
2.4 TJA1044 CAN FD (applicable to all product variants except TJA1044T)
TJA1044 CAN FD（适用于除TJA1044T以外的所有产品型号）
1）Timing guaranteed for CAN FD data rates up to 5 Mbit/s
2） Improved TXD to RXD propagation delay of 210 ns
1）CAN FD数据速率高达5 Mbit/s时依然可以保证定时正常工作
2） 将TXD到RXD的传播延迟提高210 ns
5. Block diagram
方框图
6. Pinning information
引脚信息
引脚描述：
符号 | 引脚 | 描述 |
TXD | 1 | 传输数据输入，从MCU输入给CAN总线 |
GND【1】 | 2 | 地引脚 |
VCC | 3 | 供电引脚 |
RXD | 4 | 传输数据输出，从CAN总线输出给MCU |
n.c. | 5 | TJA1044T, TJA1044GT and TJA1044GTK 型号该引脚未连接 |
VIO | 5 | TJA1044GT/3、TJA1044GTK/3型号该引脚才会连接，为IO口提供电压 |
CANL | 6 | 低电平CAN总线 |
CANH | 7 | 高电平CAN总线 |
STB | 8 | 待机模式（Standby）控制输入 |
【1】HVSON8封装芯片地线既要连接到GND引脚也要连接到外露的中心焊盘。这个
GND引脚必须焊接到电路板的地上。为了增强热性能和电气性能，建议将外露的中心焊盘也焊接到电路板地上。
7. Functional description
功能描述
7.1 Operating modes
操作模式
The TJA1044 supports two operating modes, Normal and Standby. The operating mode is
selected via pin STB. See Table 4 for a description of the operating modes under normal
supply conditions.
TJA1044支持两种工作模式：正常模式和待机模式。操作模式需要通过STB引脚来选择。正常情况下的操作模式说明见表4。
表格4：操作模式
模式 | 输入 | 输出 | ||
STB引脚 | TXD引脚 | CAN驱动器 | RXD引脚 | |
正常模式 | 低电平 | 低电平 | 显性 | 低电平 |
高电平 | 隐性 | CAN总线显性时为低电平 | ||
CAN总线隐性时为高电平 | ||||
待机模式 | 高电平 | X【忽略】 | 对地偏置 | 当检测到唤醒时跟随CAN总线 |
没有唤醒时为高电平 | ||||
7.1.1 Normal mode
正常模式
A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit
and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram).
The differential receiver converts the analog data on the bus lines into digital data which is
output on pin RXD. The slopes of the output signals on the bus lines are controlled
internally and are optimized in a way that guarantees the lowest possible EME.
引脚STB为低电平时工作模式选择为正常模式。在这种模式下，收发器可以通过总线CANH和CANL发送和接收数据。差分接收器将CAN总线上的模拟数据转换为数字数据，然后通过引脚RXD输出给MCU。CAN总线上输出信号的斜率受到内部控制，并且为了确保最低的EME进行了优化。
7.1.2 Standby mode
待机模式
A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not able to transmit or correctly receive data via the bus lines. The transmitter and Normal-mode receiver blocks are switched off to reduce supply current, and only a low-power differential receiver monitors the bus lines for activity.
In Standby mode, the bus lines are biased to ground to minimize system supply current.
The low-power receiver is supplied from VIO (VCC in non-VIO variants) and can detect CAN
bus activity even if VIO is the only available supply voltage. Pin RXD follows the bus after
a wake-up request has been detected. A transition to Normal mode is triggered when STB
is forced LOW.
引脚STB为高电平时进入待机模式。在待机模式下，收发器不能通过总线传输数据或正确接收数据。发射机和正常模式接收器模块被关闭以减少供电电流，并且只有低功率差分接收器还在活动，用于监控CAN总线。
在待机模式下，CAN总线偏置接地，使得系统电源电流最小化。低功耗接收器由VIO（没有VIO引脚的变种芯片中的VCC）提供，可以检测can总线活动，即使VIO是唯一可用的电源电压。已检测到唤醒请求时引脚RXD的电平跟随总线电平。STB引脚被强制为低电平，会触发到正常模式的转换。
7.2 Remote wake-up (via the CAN bus)
远程唤醒（通过CAN总线）
The TJA1044 wakes up from Standby mode when a dedicated wake-up pattern (specified
in ISO 11898-2:2016) is detected on the bus. This filtering helps avoid spurious wake-up
events. A spurious wake-up sequence could be triggered by, for example, a dominant
clamped bus or by dominant phases due to noise or spikes on the bus.
当使用专用唤醒模式（在ISO 11898-2:2016中指定）在总线上检测到时，TJA1044从待机模式唤醒。这种过滤有助于避免虚假的唤醒事件。一个虚假的唤醒序列可能是由一个显性钳制电压或者一个由于CAN总线上的噪声或尖峰造成的显性相位触发的。
The wake-up pattern consists of:
• a dominant phase of at least
followed by
• a recessive phase of at least
followed by
• a dominant phase of at least
唤醒模式包括：
• 一个显性相位，时长至少为
，接着是：
• 一个隐性相位，时长至少为
，接着是：
• 一个显性相位，时长至少为
Dominant or recessive bits between the above mentioned phases that are shorter than
and
respectively are ignored. 忽略上述相位中短于
和
的显性或隐性位。 The complete dominant-recessive-dominant pattern must be received within
to
be recognized as a valid wake-up pattern. Otherwise, the internal wake-up logic is reset. The complete wake-up pattern will then need to be retransmitted to trigger a wake-up event. Pin RXD remains HIGH until the wake-up event has been triggered. 完整的显性-隐性-显性模式必须在
时间内接收到，才能被识别为一个有效的唤醒模式。否则，内部唤醒逻辑将会被重置。然后需要重新传输完整的唤醒模式以触发唤醒事件。在触发唤醒事件之前，引脚RXD保持高电平。 After a wake-up sequence has been detected, the TJA1044 will remain in Standby mode
with the bus signals reflected on RXD. Note that dominant or recessive phases lasting less than
will not be detected by the low-power differential receiver and will not be reflected on RXD in Standby mode. 检测到唤醒序列后，TJA1044将保持待机模式并将总线信号反射到RXD引脚上。请注意，持续时间小于
的显性或隐性相位将不会被低功率差分接收机检测到，并且在待机模式下不会反射到RXD引脚上。
A wake-up event is not flagged on RXD if any of the following events occurs while a valid
wake-up pattern is being received:
如果在一个唤醒模式被接收到，而以下事件中的任何一个出现，则唤醒时间将不会在RXD引脚被标记：
• The TJA1044 switches to Normal mode
• The complete wake-up pattern was not received within
• A
or
undervoltage is detected (
<
or
<
;• TJA1044切换至正常模式
• 没有在
内收到完整的唤醒模式
• 一个
或者
低压被检测到 (
<
or
<
;
7.3 Fail-safe features
故障保护功能
7.3.1 TXD dominant time-out function
TXD引脚显性超时功能
A 'TXD dominant time-out' timer is started when pin TXD is set LOW. If the LOW state on
this pin persists for longer than
, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of
approximately 25 kbit/s. 引脚TXD设置为低电平时，一个“TXD引脚显性超时”计时器将被启动。如果TXD引脚上的低电平状态持续时间超过
，发送器被禁用，释放总线线到隐性状态。此功能可防止硬件和/或软件应用程序将CAN总线线路驱动到永久显性状态（阻塞所有的网络通讯）。引脚TXD设置为高电平时，TXD引脚显性超时定时器复位。TXD引脚显性超时时间还定义了最小可能比特率大约为25 kbit/s。【即发送1bit时间最长为40us，定时器时长
也为40us，如果发送1bit时间大于40us，则判断定时器超时，发送器被禁用。即比特率必须大于等于25 kbit/s】
7.3.2 Internal biasing of TXD and STB input pins
TXD和STB输入引脚的内部偏置
Pins TXD and STB have internal pull-ups to
(
for variants with a
pin) to ensure a safe, defined state in case one or both of these pins are left floating. Pull-up currents
flow in these pins in all states; both pins should be held HIGH in Standby mode to
minimize supply current. 引脚TXD和STB具有内部上拉功能，上拉到
（或者
，对于带有
引脚的芯片变种），以确保一种安全的定义的状态，以防其中一个或两个引脚都处于浮动状态。在所有状态下，上拉电流在这些引脚中流动；在待机模式下，两个引脚应保持高位，以使得电源电流最小化。7.3.3 Undervoltage detection on pins
and
引脚和
引脚的欠压检测 If
drops below the standby undervoltage detection level,
, the transceiver switches to Standby mode. The logic state of pin STB is ignored until VCC has recovered.
In versions with a
pin, if
drops below the switch-off undervoltage detection level
(
), the transceiver switches off and disengages from the bus (zero load) until
VIO has recovered.
In versions without a
pin, if
drops below the switch-off undervoltage detection
level
, the transceiver switches off and disengages from the bus (zero
load) until VCC has recovered. 如果
低于进入待机模式的欠压水平【
】，收发器将切换至待机模式。引脚STB的逻辑状态被忽略，直到
恢复到正常电压水平。 带有
引脚的芯片，如果
低于关断欠压检测水平（
），收发器关闭并与总线分离（零负载），直到
恢复到正常电压水平。 带有
引脚的芯片， 如果
低于进入待机模式的欠压水平【
】，收发器将切换至待机模式。引脚STB的逻辑状态被忽略，直到
恢复到正常电压水平。
7.3.4 Overtemperature protection
超温保护
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, Tj(sd), both output drivers are
disabled. When the virtual junction temperature drops below Tj(sd) again, the output
drivers recover once TXD has been reset to HIGH. Including the TXD condition prevents
output driver oscillation due to small variations in temperature.
输出驱动器受到过温保护。如果模拟结温度超过结关停温度Tj（sd），两个输出驱动器均被禁止。当模拟结温度再次降至Tj（sd）以下时，一旦TXD引脚重置为高电平，输出驱动就会恢复。包括TXD引脚的电平条件才恢复驱动，可防止由于温度的微小变化导致输出驱动器出现振荡，反复禁止和恢复。
7.4
supply pin (TJA1044x/3 variants)
电源引脚（TJA1044x/3 变种【TJA1044GT/3、TJA1044GTK/3】才会有该引脚） Pin
should be connected to the microcontroller supply voltage. This will adjust the signal levels of pins TXD, RXD and STB to the I/O levels of the microcontroller.Pin
also provides the internal supply voltage for the low-power differential receiver in the transceiver. For applications running in low-power mode, this allows the bus lines to be monitored for activity even if there is no supply voltage on pin
.
For variants of the TJA1044 without a
pin, all circuitry is connected to
(pin 5 is not
bonded). The signal levels of pins TXD, RXD and STB are then compatible with 5 V
microcontrollers. This allows the device to interface with both 3.3 V and 5 V-supplied
microcontrollers, provided the microcontroller I/Os are 5 V tolerant. 引脚
应连接到微控制器电源电压。这将把引脚TXD、RXD和STB的电平调整为微控制器的I/O电平。引脚
还为收发器中的低功率差分接收器提供内部电源电压。对于在低功率模式下运行的应用程序，即使
引脚上没有电源电压，也可以监控总线的活动。 对于不带
引脚的TJA1044芯片变种型号，所有电路都连接到
（引脚5未连接））。引脚TXD、RXD和STB的信号电平与5V微控制器兼容。这允许设备与3.3 V和5 V电源供电的微控制器连接，前提是微控制器I/O能承受5V。
12. Application information
应用信息
12.1 Application diagram
应用电路图
