`timescale 1ns/10ps
module RGB_YCbCr
(
Clock,
Reset,
IDEN,
IHS,
IVS,
R,
G,
B,
ODEN_RGB,
OHS_RGB,
OVS_RGB,
Y_in,
Cb_in,
Cr_in
);
//
parameter DATAWIDTH = 8;
//---------------------------------------------------------------------------------
//
input[DATAWIDTH-1:0] R;
input[DATAWIDTH-1:0] G;
input[DATAWIDTH-1:0] B;
input Clock;
input Reset;
input IDEN;
input IHS;
input IVS;
//
output ODEN_RGB;
output OHS_RGB;
output OVS_RGB;
output[DATAWIDTH+3:0]Y_in;
output[DATAWIDTH+3:0]Cb_in;
output[DATAWIDTH+3:0]Cr_in;
//*********************************************************************************
//
reg IDEN_RGB_Reg0;
reg IDEN_RGB_Reg1;
reg IDEN_RGB_Reg2;
reg ODEN_RGB;
reg IHS_RGB_Reg0;
reg IHS_RGB_Reg1;
reg IHS_RGB_Reg2;
reg OHS_RGB;
reg IVS_RGB_Reg0;
reg IVS_RGB_Reg1;
reg IVS_RGB_Reg2;
reg OVS_RGB;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
IDEN_RGB_Reg0<=1'b0;
IDEN_RGB_Reg1<=1'b0;
IDEN_RGB_Reg2<=1'b0;
ODEN_RGB<=1'b0;
end
else
begin
IDEN_RGB_Reg0<=IDEN;
IDEN_RGB_Reg1<=IDEN_RGB_Reg0;
IDEN_RGB_Reg2<=IDEN_RGB_Reg1;
ODEN_RGB<=IDEN_RGB_Reg2;
end
end
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
IHS_RGB_Reg0<=1'b0;
IHS_RGB_Reg1<=1'b0;
IHS_RGB_Reg2<=1'b0;
OHS_RGB<=1'b0;
end
else
begin
IHS_RGB_Reg0<=IHS;
IHS_RGB_Reg1<=IHS_RGB_Reg0;
IHS_RGB_Reg2<=IHS_RGB_Reg1;
OHS_RGB<=IHS_RGB_Reg2;
end
end
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
IVS_RGB_Reg0<=1'b0;
IVS_RGB_Reg1<=1'b0;
IVS_RGB_Reg2<=1'b0;
OVS_RGB<=1'b0;
end
else
begin
IVS_RGB_Reg0<=IVS;
IVS_RGB_Reg1<=IVS_RGB_Reg0;
IVS_RGB_Reg2<=IVS_RGB_Reg1;
OVS_RGB<=IVS_RGB_Reg2;
end
end
//*********************************************************************************
//
reg [DATAWIDTH-1:0] R_Reg,G_Reg,B_Reg;
//
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
R_Reg <= 8'b0;
G_Reg <= 8'b0;
B_Reg <= 8'b0;
end
else
begin
R_Reg <= R;
G_Reg <= G;
B_Reg <= B;
end
end
//********************************************************************************
wire[19:0] Y_R1;
wire[19:0] Y_R1_temp;
wire[15:0] Y_R2;
wire[19:0] Y_R_sum;
reg [19:0] Y_R1_Reg;
reg [15:0] Y_R2_Reg;
reg [19:0] Y_R_sum_Reg;
//
assign Y_R1_temp = {R_Reg,11'b0}+{R_Reg,8'b0};
assign Y_R1 = Y_R1_temp + {R_Reg,1'b0};
assign Y_R2 = {R_Reg,7'b0}+{R_Reg,4'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_R1_Reg <= 20'b0;
Y_R2_Reg <= 16'b0;
end
else
begin
Y_R1_Reg <= Y_R1;
Y_R2_Reg <= Y_R2;
end
end
//
assign Y_R_sum = Y_R1_Reg+Y_R2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_R_sum_Reg <= 20'b0;
end
else
begin
Y_R_sum_Reg <= Y_R_sum;
end
end
//-------------------------------------------------------------------------------
wire[20:0] Y_G1;
wire[20:0] Y_G1_temp;
wire[15:0] Y_G2;
wire[15:0] Y_G2_temp;
wire[20:0] Y_G_sum;
reg [20:0] Y_G1_Reg;
reg [15:0] Y_G2_Reg;
reg [20:0] Y_G_sum_Reg;
//
assign Y_G1_temp = {G_Reg,12'b0}+{G_Reg,9'b0};
assign Y_G1 = Y_G1_temp + G_Reg;
assign Y_G2_temp = {G_Reg,7'b0}+{G_Reg,6'b0};
assign Y_G2 = Y_G2_temp+{G_Reg,3'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_G1_Reg <= 21'b0;
Y_G2_Reg <= 16'b0;
end
else
begin
Y_G1_Reg <= Y_G1;
Y_G2_Reg <= Y_G2;
end
end
//
assign Y_G_sum = Y_G1_Reg+Y_G2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_G_sum_Reg <= 21'b0;
end
else
begin
Y_G_sum_Reg <= Y_G_sum;
end
end
//-------------------------------------------------------------------------------
wire[17:0] Y_B1;
wire[17:0] Y_B1_temp;
wire[16:0] Y_B2;
wire[16:0] Y_B2_temp;
wire[17:0] Y_B_sum;
reg [17:0] Y_B1_Reg;
reg [16:0] Y_B2_Reg;
reg [17:0] Y_B_sum_Reg;
//
assign Y_B1_temp = {B_Reg,9'b0}+{B_Reg,2'b0};
assign Y_B1 = Y_B1_temp+{B_Reg,1'b0};
assign Y_B2_temp ={B_Reg,8'b0}+{B_Reg,7'b0};
assign Y_B2 = {B_Reg,5'b0}+Y_B2_temp;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_B1_Reg <= 18'b0;
Y_B2_Reg <= 17'b0;
end
else
begin
Y_B1_Reg <= Y_B1;
Y_B2_Reg <= Y_B2;
end
end
//
assign Y_B_sum = Y_B1_Reg+Y_B2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Y_B_sum_Reg <= 18'b0;
end
else
begin
Y_B_sum_Reg <= Y_B_sum;
end
end
//-------------------------------------------------------------------------------
wire[21:0] Y_RGB_Sum;
wire[21:0] Y_RGB_Sum_temp;
wire[11:0] Y_RGB_Sum_limit;
reg [11:0] Y_in;
assign Y_RGB_Sum_temp = Y_R_sum_Reg+Y_G_sum_Reg;
assign Y_RGB_Sum = Y_RGB_Sum_temp+Y_B_sum_Reg;
assign Y_RGB_Sum_limit = Y_RGB_Sum[21:10];
//
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
Y_in <= 12'b0;
else
Y_in <= Y_RGB_Sum_limit[11:0];
end
//********************************************************************************
//
wire[18:0] Cb_R1;
wire[18:0] Cb_R1_temp;
wire[16:0] Cb_R2;
wire[16:0] Cb_R2_temp;
wire[18:0] Cb_R_sum;
reg [18:0] Cb_R1_Reg;
reg [16:0] Cb_R2_Reg;
reg [18:0] Cb_R_sum_Reg;
//
assign Cb_R1_temp = {R_Reg,10'b0}+{R_Reg,2'b0};
assign Cb_R1 = Cb_R1_temp+{R_Reg,1'b0};
assign Cb_R2_temp = {R_Reg,8'b0}+{R_Reg,6'b0};
assign Cb_R2 = Cb_R2_temp+{R_Reg,5'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_R1_Reg <= 19'b0;
Cb_R2_Reg <= 17'b0;
end
else
begin
Cb_R1_Reg <= Cb_R1;
Cb_R2_Reg <= Cb_R2;
end
end
//
assign Cb_R_sum = Cb_R1_Reg+Cb_R2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_R_sum_Reg <= 19'b0;
end
else
begin
Cb_R_sum_Reg <= Cb_R_sum;
end
end
//---------------------------------------------------------------------------------
//
wire[19:0] Cb_G1;
wire[19:0] Cb_G1_temp;
wire[17:0] Cb_G2;
wire[17:0] Cb_G2_temp;
wire[19:0] Cb_G_sum;
reg [19:0] Cb_G1_Reg;
reg [17:0] Cb_G2_Reg;
reg [19:0] Cb_G_sum_Reg;
assign Cb_G1_temp ={G_Reg,11'b0}+{G_Reg,3'b0};
assign Cb_G1 = Cb_G1_temp+{G_Reg,1'b0};
assign Cb_G2_temp ={G_Reg,9'b0}+{G_Reg,7'b0};
assign Cb_G2 = Cb_G2_temp+{G_Reg,4'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_G1_Reg <= 20'b0;
Cb_G2_Reg <= 18'b0;
end
else
begin
Cb_G1_Reg <= Cb_G1;
Cb_G2_Reg <= Cb_G2;
end
end
//
assign Cb_G_sum = Cb_G1_Reg+Cb_G2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_G_sum_Reg <= 20'b0;
end
else
begin
Cb_G_sum_Reg <= Cb_G_sum;
end
end
//---------------------------------------------------------------------------------
//
wire[20:0] Cb_B;
reg [20:0] Cb_B_sum;
reg [20:0] Cb_B_sum_Reg;
assign Cb_B = {B_Reg,12'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_B_sum <= 21'b0;
Cb_B_sum_Reg <= 21'b0;
end
else
begin
Cb_B_sum <= Cb_B;
Cb_B_sum_Reg <= Cb_B_sum;
end
end
//---------------------------------------------------------------------------------
//
wire[21:0] Cb_RGB_sum;
wire[20:0] Cb_RGB_sum_temp1;
wire[20:0] Cb_RGB_sum_temp2;
wire[11:0] Cb_RGB_sum_limit;
reg [11:0] Cb_in;
//
assign Cb_RGB_sum_temp1 = Cb_R_sum_Reg+Cb_G_sum_Reg;
assign Cb_RGB_sum_temp2 = Cb_B_sum_Reg;
assign Cb_RGB_sum = Cb_RGB_sum_temp2-Cb_RGB_sum_temp1;
assign Cb_RGB_sum_limit = Cb_RGB_sum[21:10]+12'd2048;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cb_in <= 12'b0;
end
else
begin
Cb_in<= Cb_RGB_sum_limit[11:0];
end
end
//*********************************************************************************
//
wire[20:0] Cr_R;
reg [20:0] Cr_R_Reg1;
reg [20:0] Cr_R_sum_Reg;
//
assign Cr_R = {R_Reg,12'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_R_Reg1 <= 21'b0;
Cr_R_sum_Reg <= 21'b0;
end
else
begin
Cr_R_Reg1 <= Cr_R;
Cr_R_sum_Reg <= Cr_R_Reg1;
end
end
//---------------------------------------------------------------------------------
//
wire[19:0] Cr_G1;
wire[19:0] Cr_G1_temp1;
wire[10:0] Cr_G1_temp2;
wire[18:0] Cr_G2;
wire[18:0] Cr_G2_temp;
wire[19:0] Cr_G_sum;
reg [19:0] Cr_G1_Reg;
reg [18:0] Cr_G2_Reg;
reg [19:0] Cr_G_sum_Reg;
assign Cr_G1_temp1={G_Reg,11'b0}+{G_Reg,8'b0};
assign Cr_G1_temp2={G_Reg,2'b0}+{G_Reg,1'b0};
assign Cr_G1 = Cr_G1_temp1+Cr_G1_temp2;
assign Cr_G2_temp = {G_Reg,10'b0}+{G_Reg,6'b0};
assign Cr_G2 = Cr_G2_temp+{G_Reg,5'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_G1_Reg <= 20'b0;
Cr_G2_Reg <= 19'b0;
end
else
begin
Cr_G1_Reg <= Cr_G1;
Cr_G2_Reg <= Cr_G2;
end
end
//
assign Cr_G_sum = Cr_G1_Reg+Cr_G2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_G_sum_Reg <= 20'b0;
end
else
begin
Cr_G_sum_Reg <= Cr_G_sum;
end
end
//---------------------------------------------------------------------------------
//
wire[17:0] Cr_B1;
wire[17:0] Cr_B1_temp;
wire[15:0] Cr_B2;
wire[17:0] Cr_B_sum;
reg [17:0] Cr_B1_Reg;
reg [15:0] Cr_B2_Reg;
reg [17:0] Cr_B_sum_Reg;
//
assign Cr_B1_temp={B_Reg,9'b0}+{B_Reg,3'b0};
assign Cr_B1 = Cr_B1_temp+{B_Reg,1'b0};
assign Cr_B2 = {B_Reg,7'b0}+{B_Reg,4'b0};
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_B1_Reg <= 18'b0;
Cr_B2_Reg <= 16'b0;
end
else
begin
Cr_B1_Reg <= Cr_B1;
Cr_B2_Reg <= Cr_B2;
end
end
//
assign Cr_B_sum = Cr_B1_Reg+Cr_B2_Reg;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_B_sum_Reg <= 18'b0;
end
else
begin
Cr_B_sum_Reg <= Cr_B_sum;
end
end
//---------------------------------------------------------------------------------
wire[21:0] Cr_sum_Reg;
wire[20:0] Cr_sum_Reg_temp1;
wire[20:0] Cr_sum_Reg_temp2;
wire[11:0] Cr_sum_Reg_limit;
reg [11:0] Cr_in;
assign Cr_sum_Reg_temp1=Cr_R_sum_Reg;
assign Cr_sum_Reg_temp2=Cr_G_sum_Reg+Cr_B_sum_Reg;
assign Cr_sum_Reg = Cr_sum_Reg_temp1-Cr_sum_Reg_temp2;
assign Cr_sum_Reg_limit = Cr_sum_Reg[21:10]+12'd2048;
always@(posedge Clock or negedge Reset)
begin
if(!Reset)
begin
Cr_in <= 12'b0;
end
else
begin
Cr_in <= Cr_sum_Reg_limit[11:0];
end
end
//**********************************************************************************
endmodule