HDLbits——Basics

Verilog Language——Basics

simple wire

Create a module with one input and one output that behaves like a wire.
1.Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog "continuous assignment" (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is "continuous" because the assignment continues all the time even if the right side's value changes. A continuous assignment is not a one-time event.
翻译如下：
与物理线不同，Verilog中的线(和其他信号)是有方向的。这意味着信息只在一个方向流动，从(通常是一个)源到汇点(源也经常被称为将值驱动到线路上的驱动器)。在Verilog的“连续赋值”(assign left_side = right_side;)中，右侧信号的值被驱动到左侧的线路上。这个赋值是“连续的”，因为即使右边的值发生了变化，赋值也一直在进行。连续分配不是一次性事件。
2.The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.
2.模块上的端口也有方向(通常是输入或输出)。输入端口是由模块外部的东西驱动的，而输出端口驱动外部模块的端口。当从模块内部查看时，输入端口是驱动程序或源，而输出端口是接收器。

3.The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. The module and port declarations create the black portions of the circuit. Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.
3.下面的图表说明了电路的每个部分是如何对应Verilog代码的每个位的。模块和端口声明创建了电路的黑色部分。您的任务是通过添加一个assign语句来连接到out来创建连接(绿色部分)。盒外的部件不是您所关心的，但是您应该知道，您的电路是通过将信号从我们的测试线束连接到您的top_module上的端口来进行测试的。

注意：输入端口的数据类型只能定义为wire类型（默认情况为wire类型），输出可以定义为reg类型

HDL描述

module top_module( input in, output out );
assign out = in;
endmodule

RTL原理图