Kind of confusing title but my assignment is to write a 4 stage MIPS processor (IF, ID, EX, WB) in a high level language (I know python best probably). Beyond the difficulty I haven't even started to try yet of caches and stalls, how do you take code that is supposed to be running in parallel and make that sequential? Consider this code snippit.
pc = 0x0
IFinput, IDinput, EXinput, WBinput = None, None, None, None
while True:
IFinput = self.memory.getInstruction(pc)
if not IFinput: #No more instructions
break
self.IF.giveInput(IFinput)
self.ID.giveInput(IDinput)
self.EX.giveInput(EXinput)
self.WB.giveInput(WBinput)
instruction += 0x4
clock += 1
IDinput = self.IF.getOutput(clock)
EXinput = self.ID.getOutput(clock)
WBinput = self.EX.getOutput(clock)
result = self.WB.getOutput(clock)
result.printToFile()
I'm trying to break apart the input and output of the thing into two different stages such that I dont "cheat" the hardware by getting output back before the "clock += 1" command executes. Is that the right way to implement this? Are there any python libraries that were written that are suited to this task? Thanks.
解决方案
Consider purpose-specific languages like VHDL or Verilog; possibly with a combination/extension such as PyHVL or Cocotb ..
.. however, if this must be created from scratch and/or a pure-Python implementation, consider using the same concepts as in the high-level hardware languages. In particular, consider a reactive design. Both Verilog and VHDL support this notion - where a change to input, such as the clock, drives the behaviors and new output state.
Each "reactive callback" then simply takes in the input state and emits a particular output state in isolation from the other components. Dependencies are then established only by state changes and reactive triggers around changes.
Things that might be used in triggers/guards:
Line or data change states
Signaling events
Cycle counts (e.g. minimum, after, random)
