Error: (vsim-3053) D:/adder/adder_controltb.v(60): Illegal output or inout port connection (port 'P0_i').
最终解决与下面几个链接虽然无关,但看了之后还是得到了启发。
http://www.edaboard.com/ftopic329717.html
http://xjhit.spaces.eepw.com.cn/articles/article/item/73905
双向总线的端口的写法等等。
标题:Verilog inout 双向口使用和仿真 转
2010-03-11 16:06:58
芯片外部引脚很多都使用inout类型的,为的是节省管腿。一般信号线用做总线等双向数据传输的时候就要用到INOUT类型了。就是一个端口同时做输入和输出。 inout在具体实现上一般用三态门来实现。三态门的第三个状态就是高阻'Z'。当inout端口不输出时,将三态门置高阻。这样信号就不会因为两端同时输出而出错了,更详细的内容可以搜索一下三态门tri-state的资料.
2 编写测试模块时,对于inout类型的端口,需要定义成wire类型变量,而其它输入端口都定义成reg类型,这两者是有区别的.
3 else,in RTL 对双向口,我们可以将其理解为2个分量:一个输入分量,一个输出分量。另外还需要一个控制信号控制输出分量何时输出。此时,我们就可以很容易地对双向端口建模。 例子:
可见,此时input_of_inout和output_of_inout就可以当作普通信号使用了。
4.仿真(o(∩_∩)o...哈哈,这才是我想要看的) 在仿真的时候,需要注意双向口的处理。如果是直接与另外一个模块的双向口连接,那么只要保证一个模块在输出的时候,另外一个模块没有输出(处于高阻态)就可以了。 很多初学者在写testbench进行仿真和验证的时候,被inout双向口难住了。仿真器老是提示错误不能进行。下面是我个人对inout端口写testbench仿真的一些总结,并举例进行说明。在这里先要说明一下inout口在testbench中要定义为wire型变量。 先假设有一源代码为:
方法一:使用相反控制信号inout口,等于两个模块之间用inout双向口互连。这种方法要注意assign 语句只能放在initial和always块内。
方法二:使用force和release语句,但这种方法不能准确反映双向端口的信号变化,但这种方法可以反在块内。
仿真 很多读者反映仿真双向端口的时候遇到困难,这里介绍一下双向端口的仿真方法。一个典型的双向端口如图1所示。
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http://xjhit.spaces.eepw.com.cn/articles/trackback/item/73905
Inout Error When Designing A Counter Test Bench
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vsim 3015
I am designing a 4-bit counter with enable, load, reset, input data, output Y, and an overflow flag RCA. Here is my code:
Code:
module counter(clk, data, Y, RCA, load, reset, enable);
input clk;
input [3:0]data;
input load;
input reset;
input enable;
output [3:0]Y = 4'b0000;
output RCA = 0;
reg [3:0]Y;
reg RCA;
wire reset = 1'b0;
always @ (negedge clk)
begin
RCA = 0;
if (reset == 1'b1)
begin
if (Y[3:0] < 4'b1111)
begin
if (load == 1'b1)
Y[3:0] = data[3:0];
else if (enable == 1'b0)
Y[3:0] = Y[3:0] + 4'b0001;
else
Y[3:0] = Y[3:0];
end
else
RCA = 1'b1;
Y[3:0] = 4'b0000;
end
else
Y[3:0] = 4'b0000;
end
endmodule
Here is the test bench I wrote for the counter:
Code:
module counter_test;
reg reset;
reg clk;
reg load;
reg enable;
reg [3:0]data;
wire RCA;
wire [3:0]Y;
counter counter0(clk,Y,reset,enable,load,RCA,data);
initial clk = 0;
always
#10 clk = ~clk;
counter counter1(clk,Y,reset,enable,load,RCA,data);
initial begin
reset = 0;
load = 1;
enable = 1;
data[3:0] = 4'b0110;
#25;
reset = 1;
#20;
load = 0;
#40;
enable = 0;
#20;
enable = 1;
end
endmodule
The programs compile fine, but I am getting the following warnings and errors during simulation:
Code:
** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'Y').
# Region: /counter_test/counter0
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
# Region: /counter_test/counter0
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'RCA').
# Region: /counter_test/counter0
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
# Region: /counter_test/counter0
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'Y').
# Region: /counter_test/counter1
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
# Region: /counter_test/counter1
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'RCA').
# Region: /counter_test/counter1
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
# Region: /counter_test/counter1
error: (vsim-3053)
Originally Posted by
fjrrulz
/.../
you have a different order of ports in module
description and in instantiation;
do not assume if the names are the same they
will be connected correctly;
either change the order or use:
.clk(clk), .data(data), ...
and it's not clear for me why you implement
the counter twice;
---
** error: (vsim-3053
Change the counters instantiation in the testbench to :
counter counter0(clk, data, Y0, RCA0, load, reset, enable);
counter counter1(clk, data, Y1, RCA1, load, reset, enable);
You have used the same o/p name for the two counters as Y and RCA which would give u a conflict , there is alos one more thing which u should take care, u have used ordered port mapping and the order of the port mapping is not the same as that of u r module declaration which is dangerous some times and thats the reason for those warnings.
Plz declare YO,Y1 and RCA0,RCA1 and rerun the simulation and u should not see any warnings.
counter with testbench
Wow, it was the order of the ports. EXTREMELY stupid mistake. Thanks guys.
Added after 3 hours 7 minutes:
OK, so the counter and test bench are posted above. I now have to combine 2 of these 4-bit counters to make an 8-bit counter. Does anyone know how to implement this? I know I have to connect the RCA flag of the first counter to the enable input of the second counter. But, how do I connect two modules together?