5月6日

a) 异步复位

b) 同步复位

input clk, rst_n; output [3:0] o_cnt;

Verilog实现代码：

module count_2(    input clk,    input rst_n,    output reg [3:0] o_cnt)    always @ (posedge clk or negedge rst_n) begin //异步复位        if(!rst_n) begin            o_cnt <= 4'b0000;         end        else if(o_cnt == 4'b1111) begin            o_cnt <= 4'b0000;        end        else begin            o_cnt <= o_cnt + 4'b0001;        end    end    /*    always @ (posedge clk) begin //同步复位        if(!rst_n) begin            o_cnt <= 4'b0000;        end        else if(o_cnt == 4'b1111) begin            o_cnt <= 4'b0000;        end        else begin            o_cnt <= o_cnt + 4'b0001;        end    end    */endmodule

module count_tb(    );        reg clk, rst_n;    wire [3:0] o_cnt;        //generate system clock with the period == 2ns;    always begin        #1 clk = ~clk;    end    initial begin        clk = 0;    end        //initialization    initial begin    rst_n = 0;    #4    rst_n = 1;        #32    rst_n = 0;    #4    rst_n = 1;        end        //Instantiation    count_2 u0(    .clk(clk),    .rst_n(rst_n),    .o_cnt(o_cnt)    );            endmodule

RTL原理图：

2. 用verilog实现4bit约翰逊(Johnson)计数器。

Verilog代码：

timescale 1ns / 1psmodule count_tb(    );        reg clk, rst_n;    wire [3:0] o_cnt;        //generate system clock with the period == 2ns;    always begin        #1 clk = ~clk;    end    initial begin        clk = 0;    end        //initialization    initial begin    rst_n = 0;    #4    rst_n = 1;        #32    rst_n = 0;    #4    rst_n = 1;        end        //Instantiation    count_johnson u0(    .clk(clk),    .rst_n(rst_n),    .o_cnt(o_cnt)    );            endmodule

timescale 1ns / 1psmodule count_tb(    );        reg clk, rst_n;    wire [3:0] o_cnt;        //generate system clock with the period == 2ns;    always begin        #1 clk = ~clk;    end    initial begin        clk = 0;    end        //initialization    initial begin    rst_n = 0;    #4    rst_n = 1;        #32    rst_n = 0;    #4    rst_n = 1;        end        //Instantiation    count_johnson u0(    .clk(clk),    .rst_n(rst_n),    .o_cnt(o_cnt)    );            endmodule

RTL原理图：

3. 用verilog实现4bit环形计数器：复位有效时输出0001，复位释放后依次输出0010，0100，1000，0001，0010...

Verilog描述：

timescale 1ns / 1psmodule count_circle(    input clk,    input rst_n,    output reg [3:0] o_cnt    );        always @ (posedge clk or negedge rst_n) begin        if(!rst_n) begin            o_cnt <=4'b0001;         end        else begin            o_cnt <= {o_cnt[2:0],o_cnt[3]};        end        end                endmodule

timescale 1ns / 1psmodule count_tb(    );        reg clk, rst_n;    wire [3:0] o_cnt;        //generate system clock with the period == 2ns;    always begin        #1 clk = ~clk;    end    initial begin        clk = 0;    end        //initialization    initial begin    rst_n = 0;    #4    rst_n = 1;        #32    rst_n = 0;    #4    rst_n = 1;        end        //Instantiation    count_circle u0(    .clk(clk),    .rst_n(rst_n),    .o_cnt(o_cnt)    );            endmodule

RTL原理图：

4. 比较一下以上三种计数器的特点。

5. 记录1,2,3题目使用的工具，操作步骤，以及出现的错误和提示信息。