Abstract

基本的4位元加法器,使用Verilog與megafuction實現。

Introduction
使用環境:Quartus II 7.2 SP3 + ModelSim-Altera 6.1g + DE2(Cyclone II EP2C35F672C6)

Method 1:
自己撰寫Verilog

add_4_v.v / Verilog

1 /* 

2 (C) OOMusou 2008 http://oomusou.cnblogs.com

4 Filename    : add_4_v.v

5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g

6 Description : Demo how to write 4 bit full adder

7 Release     : 07/11/2008 1.0

8 */

9 module add_4_v (

10   input  [3:0] a,

11   input  [3:0] b,

12   input        ci,

13   output [3:0] s,

14   output       co

15 );

16 

17 wire [2:0] carry;

18 

19 function fa_s(input a, input b, input ci);

20   fa_s = a ^ b ^ ci;

21 endfunction

22 

23 function fa_co(input a, input b, input ci);

24   fa_co = a & ci | a & b | b & ci;

25 endfunction

26 

27 assign s[0]     = fa_s (a[0], b[0], ci);

28 assign carry[0] = fa_co(a[0], b[0], ci);

29 

30 assign s[1]     = fa_s (a[1], b[1], carry[0]);

31 assign carry[1] = fa_co(a[1], b[1], carry[0]);

32 

33 assign s[2]     = fa_s (a[2], b[2], carry[1]);

34 assign carry[2] = fa_co(a[2], b[2], carry[1]);

35 

36 assign s[3]     = fa_s (a[3], b[3], carry[2]);

37 assign co       = fa_co(a[3], b[3], carry[2]);

38 

39 endmodule

Method 2:
使用Megafunction : lpm_add_sub

add_4_v2.v / Verilog

1 /* 

2 (C) OOMusou 2008 http://oomusou.cnblogs.com

4 Filename    : add_4_v2.v

5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g

6 Description : Demo how to write 4 bit full adder by megafunction

7 Release     : 07/11/2008 1.0

8 */

9 module add_4_v2 (

10   input  [3:0] a,

11   input  [3:0] b,

12   input        ci,

13   output [3:0] s,

14   output       co

15 );

16 

17 lpm_add_sub # (.lpm_width(4))

18 u0 (

19  .dataa(a),

20  .datab(b),

21  .result(s),

22  .cout(co)

23 );

24 endmodule

Testbench
add_4_v_tb.v / Verilog

1 /* 

2 (C) OOMusou 2008 http://oomusou.cnblogs.com

4 Filename    : add_4_v.v

5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g

6 Description : Demo how to write 4 bit full adder testbench

7 Release     : 07/11/2008 1.0

8 */

9 `timescale 1ns/10ps

10 module add_4_v_tb;

11 reg [3:0] a;

12 reg [3:0] b;

13 reg      ci;

14 

15 wire [3:0] s;

16 wire       co;

17 

18 add_4_v2 u0 (

19   .a(a),

20   .b(b),

21   .ci(ci),

22   .s(s),

23   .co(co)

24 );

25 

26 initial begin

27 a  = 4'h0;

28 b  = 4'h0;

29 ci = 4'h0;

30 end

31 

32 always #50  a = a + 1;

33 always #100 b = a + 1;

34 

35 endmodule

(筆記) 如何設計4位元的加法器? (SOC) (Verilog) (MegaCore)_加法器